This invention relates to digital signal translators which convert digital signals from one pair of voltage levels to another; and in particular, it relates to circuits for use in such translators which make their operation insensitive to threshold voltage variations in their transistors.
In the prior art, digital signal translators exist which convert digital input signals that have CMOS voltage levels into digital output signals that have ECL voltage levels. CMOS voltage levels nominally are zero volts and +5 volts; and the corresponding ECL voltage levels nominally are -0.9 volts and -1.8 volts. However, the prior art translators are deficient in that the ECL voltage levels of their output signals vary too widely with changes in the threshold voltage of the transistors from which the translators are made. When the threshold voltage variations cause the two voltage levels of the output signal to move closer together, then the two levels are less distinguishable from each other. Conversely, when the two voltage levels of the output signal move farther apart, then switching noise is increased as the signal changes from one level to the other.
This problem cannot be overcome simply by making the threshold voltage of the transistors fixed. That is because the threshold voltage shifts are caused by unavoidable variations in the processes which make the transistors. For example, variations in the process step which etches the transistor's gate will change the gate length. An etch which yields a nominal gate length will tend to produce a transistor with a nominal threshold voltage; an etch which yields a longer gate will tend to increase the threshold voltage; and an etch which yields a shorter gate will tend to decrease the threshold voltage. These variations will affect the threshold of both P-channel transistors and N-channel transistors since their gates are etched with the same step.
Other processing variations can affect the threshold of N-channel transistors and the threshold of P-channel transistors independently. For example, the source and drain of the N-channel transistors are implanted separately from the source and drain of the P-channel transistors since they require different type dopants. And, an implant dosage which is larger than nominal will shorten the effective channel length and tend to produce a lower threshold voltage; whereas an implant dosage which is smaller than nominal will increase the effective channel length and tend to raise the threshold voltage. Further, N-channel transistors and/or P-channel transistors sometimes have their channel implanted separately to shift their threshold up or down, and the dosage of such channel implants has an unavoidable tolerance which varies above and below a nominal value.
Accordingly, a primary object of the invention is to provide a circuit, for use with digital signal translators, by which the above described problems are avoided.